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Title: Semiconductor storage
Abstract: It is an object to obtain a semiconductor storage having a 1—chip structure which can be simultaneously accessed to memory cells present in different memory cell arrays. A 1-port memory cell array (11) provided with a word line (WL1) for a first port in common and a 2-port memory cell array (12) are provided together over one chip, thereby constituting a semiconductor storage. By selectively bringing any of a plurality of the word lines (WL1) for the first port into an active state by a row decoder (16), it is possible to simultaneously access respective memory cells of the 1-port memory cell array (11) and the 2-port memory cell array (12). By selectively bringing any of a plurality of word lines (WL2) for a second port into an active state by a row decoder (18), it is possible to singly access the 2-port memory cell array (12).
Patent Number: 7,024,524 Issued on 04/04/2006 to Nii
| Inventors:
|
Nii; Koji (Tokyo, JP)
|
| Assignee:
|
Renesas Technology Corp. (Tokyo, JP)
|
| Appl. No.:
|
454500 |
| Filed:
|
June 5, 2003 |
Foreign Application Priority Data
| Dec 10, 2002[JP] | 2002-357630 |
| Current U.S. Class: |
711/154; 711/100; 711/117; 711/123; 711/136 |
| Current Intern'l Class: |
G06F 12/00 (20060101) |
| Field of Search: |
711/100,111,131,149,150,154,156,117,118,123,125,136
365/189.01,233,239
|
References Cited [Referenced By]
U.S. Patent Documents
| 4964083 | Oct., 1990 | Nogle et al.
| |
| 5067111 | Nov., 1991 | Asano et al.
| |
| 6144055 | Nov., 2000 | Takenaka.
| |
| 6169684 | Jan., 2001 | Takahashi et al.
| |
| 6195278 | Feb., 2001 | Calin et al.
| |
| 6229758 | May., 2001 | Agata.
| |
| Foreign Patent Documents |
| 6-349275 | Dec., 1994 | JP.
| |
| 10-178110 | Jun., 1998 | JP.
| |
Primary Examiner: Thai; Tuan V.
Attorney, Agent or Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
Claims
What is claimed is:
1. A semiconductor storage comprising first and second memory cell arrays,
said first memory cell array including:
a plurality of first memory cells arranged in at least one column over a plurality
of rows; and
a plurality of first word lines to be connected to said first memory cells on
a row unit,
said second memory cell array including:
a plurality of second memory cells arranged in a matrix, said second memory cells
including a different number of elements than said first memory cells;
a plurality of second word lines to be connected to said second memory cells
on a row unit;
a plurality of third word lines connected to said second memory cells on a row
unit and not connected to any of said plurality of first memory cells;
a plurality of first bit lines provided corresponding to said second memory cells
on a column unit and being accessible to said second memory cell connected to said
second word line in a selection state out of said plurality of second word lines; and
a plurality of second bit lines provided corresponding to said second memory
cells on a column unit and being accessible to said second memory cell connected
to said third word line in a selection state out of said plurality of third word lines,
said semiconductor storage further comprising:
a first row decoder configured to select, so that a period wherein any of said
first word lines is brought into a selection state based on a first address signal
and a period wherein any of said second word lines is brought into a selection
state based on said first address signal are overlapped.
2. The semiconductor storage according to claim 1, wherein
said first memory cells include a plurality of memory cells arranged in a matrix; and
said first and second word lines include a plurality of common word line to be
shared on a row unit.
3. The semiconductor storage according to claim 1, wherein
said first memory cells include a plurality of memory cells arranged in a matrix; and
said first row decoder is provided between said first and second memory cell arrays.
4. The semiconductor storage according to claim 1, wherein
said first and second memory cells include circuit structures having different
port structures from each other.
5. The semiconductor storage according to claim 4, wherein
said first memory cell includes a memory cell having a 1-port structure which
can be accessed by only a first port,
said second memory cell includes a memory cell having a 2-port structure which
can be accessed by said first port and a second port, and
an access to be carried out by said first row decoder in a selection state of
said first and second word lines includes an access to be preformed by said first port.
6. The semiconductor storage according to claim 5, further comprising:
a second row decoder for bringing any of said plurality of said third word lines
into a selection state based on a second address signal,
an access to be carried out by said second row decoder in a selection state of
said third word line including an access to be performed by said second port.
7. The semiconductor storage according to claim 5, wherein
said second memory cell includes a memory cell having a 2-port structure in which
reading and writing can be carried out by said second port.
8. The semiconductor storage according to claim 5, wherein
said second memory cell includes a content addressable memory cell in which a
comparison result between an expected value given from an outside and self-stored
contents can be output from said second port.
9. The semiconductor storage according to claim 5, wherein
said second memory cell includes a memory cell having a 2-port structure in which
only reading using said second port can be carried out.
10. The semiconductor storage according to claim 5, wherein
said first memory cell and said second memory cell have cell heights to be formation
lengths in a predetermined direction on a layout structure which are set to be
equal to each other.
11. The semiconductor storage according to claim 4, further comprising:
a second row decoder for bringing any of said plurality of said third word lines
into a selection state based on a second address signal, wherein
said first memory cell includes a memory cell having a 2-port structure which
can be accessed by a first port and a second port,
said second memory cell including a memory cell having a 2-port structure which
can be accessed by said first port and a third port which is different from said
second port,
an access to be carried out by setting said first and second word lines into
a selection state by said first row decoder including an access to be performed
by said first port, and
an access to be carried out by setting said third word line into a selection
state by said second decoder including an access to be performed by said third port.
12. The semiconductor storage according to claim 1, wherein
said plurality of first memory cells include a plurality of first dummy cells
and said plurality of second memory cells include a plurality of memory cells for
a real operation,
said plurality of first and second word lines include a plurality of common word
lines to be shared on a row unit, and
the number of accessible ports of said first dummy cells is set to be smaller
than that of accessible ports of said memory cells for a real operation.
13. The semiconductor storage according to claim 12, further comprising:
a second row decoder for bringing any of said plurality of third word lines into
a selection state based on a second address signal; and
a third memory cell array having a plurality of second dummy cells arranged in
at least a column over a plurality of rows, said first and third memory cell arrays
being formed integrally with said second memory cell array interposed therebetween
and the number of accessible ports of said second dummy cell being set to be smaller
than that of accessible ports of said memory cells for a real operation,
said memory cells for a real operation including a memory cell having a 2-port
structure with first and second ports which are accessible,
said first and second dummy cells including a memory cell having a 1-port structure
with first and second dummy ports which are accessible,
said first ports of said plurality of memory cells for a real operation and said
first dummy ports of said plurality of first dummy cells being connected to said
plurality of common word lines on a row unit in common,
said second ports of said plurality of memory cells for a real operation and
said second dummy ports of said plurality of second dummy cells being connected
to said plurality of third word lines on a row unit in common,
said first row decoder including a row decoder provided in the vicinity of said
first memory cell array, and
said second row decoder including a row decoder provided in the vicinity of said
third memory cell array.
14. The semiconductor storage according to claim 13, wherein
said first and second dummy cells include a memory cell for reading timing regulation
with respect to said memory cell for a real operation.
15. A semiconductor storage comprising first and second memory cell arrays,
said first memory cell array including:
a plurality of first memory cells arranged in at least one column over a plurality
of rows; and
a plurality of first word lines to be connected to said first memory cells on
a row unit,
said second memory cell array including:
a plurality of second memory cells arranged in a matrix;
a plurality of second word lines to be connected to said second memory cells
on a row unit;
a plurality of third word lines connected to said second memory cells on a row
unit and not connected to any of said plurality of first memory cells;
a plurality of first bit lines provided corresponding to said second memory cells
on a column unit and being accessible to said second memory cell connected to said
second word line in a selection state out of said plurality of second word lines; and
a plurality of second bit lines provided corresponding to said second memory
cells on a column unit and being accessible to said second memory cell connected
to said third word line in a selection state out of said plurality of third word lines,
said semiconductor storage further comprising:
a first row decoder for simultaneously bringing any of said first word lines
and any of said second word lines into a selection state based on a first address signal;
a second row decoder for bringing any of said plurality of third word lines into
a selection state based on a second address signal; and
a third memory cell array having a plurality of second dummy cells arranged in
at least a column over a plurality of rows, said first and third memory cell arrays
being formed integrally with said second memory cell array interposed therebetween
and the number of accessible ports of said second dummy cell being set to be smaller
than that of accessible ports of said memory cells for a real operation,
said memory cells for a real operation including a memory cell having a 2-port
structure with first and second ports which are accessible,
said first and second dummy cells including a memory cell having a 1-port structure
with first and second dummy ports which are accessible,
said first ports of said plurality of memory cells for a real operation and said
first dummy ports of said plurality of first dummy cells being connected to said
plurality of common word lines on a row unit in common,
said second ports of said plurality of memory cells for a real operation and
said second dummy ports of said plurality of second dummy cells being connected
to said plurality of third word lines on a row unit in common,
said first row decoder including a row decoder provided in the vicinity of said
first memory cell array, and
said second row decoder including a row decoder provided in the vicinity of said
third memory cell array.
16. The semiconductor storage according to claim 15, wherein
said first and second dummy cells include a memory cell for reading timing regulation
with respect to said memory cell for a real operation.
17. A semiconductor storage comprising first and second memory cell arrays,
said first memory cell array including:
a plurality of first memory cells arranged in at least one column over a plurality
of rows; and
a plurality of first word lines to be connected to said first memory cells on
a row unit,
a plurality of second word lines to be connected to said first memory cells on
a row unit,
a plurality of first bit lines provided corresponding to said first memory cells
on a column unit and being accessible to said first memory cell connected to said
first word line in a selection state out of said plurality of first word lines; and
a plurality of second bit lines provided corresponding to said first memory cells
on a column unit and being accessible to said first memory cell connected to said
second word line in a selection state out of said plurality of second word lines,
said second memory cell array including:
a plurality of second memory cells arranged in a matrix, said second word lines
not being connected to any of said second memory cells;
a plurality of third word lines to be connected to said second memory cells on
a row unit;
a plurality of fourth word lines connected to said second memory cells on a row
unit and not connected to any of said first memory cells;
a plurality of third bit lines provided corresponding to said second memory cells
on a column unit and being accessible to said second memory cell connected to said
third word line in a selection state out of said plurality of third word lines; and
a plurality of fourth bit lines provided corresponding to said second memory
cells on a column unit and being accessible to said second memory cell connected
to said fourth word line in a selection state out of said plurality of fourth word lines,
said semiconductor storage further comprising:
a first row decoder configured to select so that a period wherein any of said
first word lines is brought into a selection state based on a first address signal
and a period wherein any of said third word lines is brought into a selection state
based on said first address signal are overlapped,
a second row decoder configured to bring any of said of second word lines into
a selection state based on a second address signal; and
a third row decoder configured to bring any of said of fourth word lines into
a selection state based on a third address signal, wherein
said first memory cell includes a memory cell having a 2-port structure which
can be accessed by a first port and a second port,
said second memory cell including a memory cell having a 2-port structure which
can be accessed by said first port and a third port which is different from said
second port,
an access to be carried out by setting said first and third word lines into a
selection state by said first row decoder including an access to be preformed by
said first port,
an access to be carried out by setting said second word line into a selection
state by said second row decoder including an access to be performed by said second
port, and
an access to be carried out by setting said fourth word line into a selection
state by said third row decoder including an access to be performed by said third port.
18. The semiconductor storage according to claim 17, wherein
said second and third row decoders are arranged with said first and second memory
cell arrays interposed therebetween.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor storage and more particularly
to a combination of a plurality of memory cell structures of an MOS static RAM.
2. Description of the Background Art
For a semiconductor storage comprising plural kinds of memory cells having different
port structures and the like, conventionally, a semiconductor storage has been
disclosed in Patent Document 1 (Japanese Patent Application Laid-Open No. 6-349275
(1994) gazette), for example. The semiconductor storage comprises a 3-port cell
section which is 3-port simultaneous accessible and a 1-port cell section having
one access port, and can be implemented by connecting them to at least a pair of
bit lines in common.
On the other hand, it has been demanded that data to be accessed on a bit length
unit are divided on a several-bit unit and individual data are accessed on the
several-bit unit thus obtained by the division in a computer field or the like.
Moreover, it has also been demanded that a part of bits are constituted to be accessible
from a plurality of ports.
In the semiconductor storage of the Patent Document 1 described above, however,
the 3-port cell section and the 1-port cell section share a bit line. For this
reason, there is a problem in that both of the port cell sections cannot be accessed
at the same time and the demand cannot be met.
SUMMARY OF THE INVENTION
It is an object of the present invention to obtain a semiconductor storage having
a one-chip structure in which memory cells present in different memory cell arrays
can be accessed at the same time.
According to the present invention, a semiconductor storage includes first
and second memory cell arrays and a first row decoder, and the first memory cell
array includes a plurality of first memory cells and a plurality of first word
lines. The plurality of first memory cells are arranged in at least one column
over a plurality of rows and the plurality of first word lines are connected to
the first memory cells on a row unit. On the other hand, the second memory cell
array includes a plurality of second memory cells, a plurality of second and third
word lines, and a plurality of first and second bit lines. The plurality of second
memory cells are arranged in a matrix, the second word lines are connected to the
second memory cells on a row unit, the plurality of third word lines are connected
to the second memory cells on a row unit and are not connected to any of the plurality
of first memory cells, and the plurality of first bit lines are provided corresponding
to the second memory cells on a column unit and are accessible to the second memory
cell connected to the second word line in a selection state out of the plurality
of second word lines, and the plurality of second bit lines are provided corresponding
to the second memory cells on a column unit and are accessible to the second memory
cell connected to the third word line in a selection state out of the plurality
of third word lines. The first row decoder simultaneously brings any of the first
word lines and any of the second word lines into the selection state based on a
first address signal.
The first and second memory cell arrays can be controlled by the first row decoder.
Consequently, it is possible to obtain a semiconductor storage having a 1-chip
structure which can be accessed to the first and second memory cells at the same time.
These and other objects, features, aspects and advantages of the present invention
will become more apparent from the following detailed description of the present
invention when taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing a structure of a semiconductor storage according
to a first embodiment of the present invention,
FIG. 2 is a circuit diagram showing a memory cell array structure according
to the first embodiment,
FIG. 3 is an explanatory view showing a layout structure provided under a first
aluminum wiring layer in a 1-port memory cell as seen on a plane,
FIG. 4 is an explanatory view showing a layout structure provided above a second
aluminum wiring layer in the 1-port memory cell,
FIG. 5 is an explanatory view showing a layout structure provided under a first
aluminum wiring layer in a 2-port memory cell as seen on a plane,
FIG. 6 is an explanatory view showing a layout structure provided above the
second aluminum wiring layer in the 2-port memory cell,
FIG. 7 is an explanatory view showing a layout structure provided under a first
aluminum wiring layer in a 1-port and 2-port memory cell as seen on a plane,
FIG. 8 is a block diagram showing a structure of a semiconductor storage according
to a second embodiment of the present invention,
FIG. 9 is a block diagram showing a structure of a semiconductor storage according
to a third embodiment of the present invention,
FIG. 10 is an explanatory diagram showing an internal structure of a row decoder
in FIG. 9,
FIG. 11 is a block diagram showing a structure of a semiconductor storage according
to a fourth embodiment of the present invention,
FIG. 12 is a circuit diagram showing a memory cell array structure according
to the fourth embodiment,
FIG. 13 is a circuit diagram showing the details of a CAM memory cell,
FIG. 14 is an explanatory view showing a layout structure of all layers in the
CAM memory cell as seen on a plane,
FIG. 15 is an explanatory view showing a layout structure provided under a first
aluminum wiring layer in FIG. 14 as seen on a plane,
FIG. 16 is an explanatory view showing a layout structure provided above a second
aluminum wiring layer in FIG. 14 as seen on a plane,
FIG. 17 is a block diagram showing a structure of a semiconductor storage according
to a fifth embodiment of the present invention,
FIG. 18 is a circuit diagram showing a memory cell array structure according
to the fifth embodiment,
FIG. 19 is a block diagram showing a structure of a semiconductor storage according
to a sixth embodiment of the present invention,
FIG. 20 is a circuit diagram showing a structure of a 2-port memory cell according
to the sixth embodiment,
FIG. 21 is an explanatory view showing a layout structure of all layers of the
2-port memory cell according to the sixth embodiment as seen on a plane,
FIG. 22 is an explanatory view showing a layout structure provided under a first
aluminum wiring layer in FIG. 21 as seen on a plane,
FIG. 23 is an explanatory view showing a layout structure provided above the
first aluminum wiring layer in FIG. 21 as seen on a plane,
FIG. 24 is a block diagram showing a structure of a semiconductor storage according
to a seventh embodiment of the present invention,
FIG. 25 is a circuit diagram showing a structure of a dummy cell formed in a
memory cell area for timing regulation, and
FIG. 26 is a circuit diagram showing a memory cell array structure according
to the seventh embodiment.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
<First Embodiment>
(Whole Structure)
FIG. 1 is a block diagram showing a structure of a semiconductor storage according
to a first embodiment of the present invention, As shown in FIG. 1, a 1-port memory
cell array 11 (a first memory cell array) and a 2-port memory cell array
12 (a second memory cell array) are provided together over one chip to constitute
a memory macro. More specifically, the 1-port memory cell array 11 is provided
with a word line WL1 for a first port (a first word line (a common word
line)) and the 2-port memory cell array 12 is provided with a word line
WL1 for a first port (a second word line (a common word line)) and a word
line WL2 for a second port (a third word line).
Upon receipt of an address input bus signal AD1, a control circuit 31
supplies a row address to a row decoder 16 (a first row decoder) and a column
address to column selectors 21 and 22 under timing control of a read
control input signal RE1 and a write control input signal WE1.
Upon receipt of an address input bus signal AD2, a control circuit 32
supplies a row address to a row decoder 17 (a second row decoder) and a
column address to a column selector 23 under timing control of a read control
input signal RE2 and a write control input signal WE2.
The row decoder 16 selectively sets any of a plurality of the word lines
WL1 for the first port into an active state (a selection state) based on
the row address and the row decoder 17 selectively sets any of a plurality
of the word lines WL2 for the second port into the active state based on
the row address.
The column selector 21 selects a portion equivalent to 4 bits from a plurality
of bit line pairs BL1 and bar BL1 for the first port based on the
column address sent from the control circuit 31 and inputs/outputs a data
input/output bus signal DIO11<7:4> to/from the 1-port
memory cell array 11 through the bit line pair BL1 and bar BL1
for the first port thus selected.
The column selector 22 selects a portion equivalent to 4 bits from a plurality
of bit line pairs BL21 and bar BL21 for the first port (first bit
lines) based on the column address sent from the control circuit 31 and
inputs/outputs a data input/output bus signal DIO12<3:0>
to/from the 2-port memory cell array 12 through the bit line pairs BL21
and bar BL21 for the first port thus selected.
The column selector 23 selects a portion equivalent to 4 bits from
a plurality of bit line pairs BL22 and bar BL22 for the second port
(second bit lines) based on the column address sent from the control circuit 32
and inputs/outputs a data input/output bus signal DIO2<3:0>
to/from the 2-port memory cell array 12 through the bit line pairs BL22
and bar BL22 for the second port thus selected.
These column selectors 22 to 24 have a sense amplifier (SA) function
and a write driving (WD) function.
(Memory Cell Structure)
FIG. 2 is a circuit diagram showing a memory cell array structure of the 1-port
memory cell array 11 and the 2-port memory cell array 12. For convenience
of explanation, FIG. 2 shows only a 2×2 memory cell but does not imply an
actual size of the memory cell array (a matrix-like memory cell arrangement).
The 1-port memory cell array 11 is constituted by memory cells ms00,
ms01, ms10 and ms11.
Each of the memory cells ms00 to ms11 is constituted by inverters
41 and 42 which are cross connected to each other, an NMOS transistor
Q11 having one of electrodes connected to an input of the inverter 41
(an output of the inverter 42), and an NMOS transistor Q12 having
one of electrodes connected to an input of the inverter 42 (an output of
the inverter 41).
Word lines WL1<0> and WL1<1>
for the first port are driven by drivers 52 and 51 (which are usually
provided in the row decoder 16 (not shown)), respectively.
In the memory cells ms00 and ms01 on the same row, gate electrodes
of the NMOS transistors Q11 and Q12 are electrically connected to
the word line WL1<0> for the first port in common. In the
memory cells ms10 and ms11 on the same row, gate electrodes of the
NMOS transistors Q11 and Q12 are electrically connected to the word
line WL1<1> for the first port in common.
Both of the memory cells ms00 and ms10 on the same column are
provided between a bit line pair BL1<0> and bar BL1<0>
for the first port. In these memory cells ms00 and ms10, the other
electrode of the NMOS transistor Q11 is electrically connected to the bit
line BL1<0> for the first port and the other electrode
of the NMOS transistor Q12 is electrically connected to the inverted bit
line bar BL1<0> for the first port.
Both of the memory cells ms01 and ms11 on the same column are
provided between a bit line pair BL1<1> and bar BL1<1>
for the first port. In the memory cells ms01 and ms11, the other
electrode of the NMOS transistor Q11 is electrically connected to the bit
line BL1<1> for the first port and the other electrode
of the NMOS transistor Q12 is electrically connected to the inverted bit
line bar BL1<1> for the first port.
On the other hand, the 2-port memory cell array 12 is constituted by memory
cells md00, md01, md10 and md11.
Each of the memory cells md00 to md11 is constituted by the inverters
41 and 42 which are cross connected to each other, NMOS transistors
Q11 and Q21 having electrodes connected to the input of the inverter
41, and NMOS transistors Q12 and Q22 having electrodes connected
to the input of the inverter 42.
Word lines WL2<0> and WL2<1>
for the second port are driven by drivers 54 and 53 (which are usually
provided in the row decoder 17 (not shown)), respectively.
In the memory cells md00 and md01 on the same row, gate electrodes
of the NMOS transistors Q11 and Q12 are electrically connected to
the word line WL1<0> for the first port in common, and
gate electrodes of the NMOS transistors Q21 and Q22 are electrically
connected to the word line WL2<0> for the second port in common.
In the memory cells md10 and md11 on the same row, gate electrodes
of the NMOS transistors Q11 and Q12 are electrically connected to
the word line WL1<1> for the first port in common, and
gate electrodes of the NMOS transistors Q21 and Q22 are electrically
connected to the word line WL2<1> for the second port in common.
Both of the memory cells md00 and md10 on the same column are
provided between a bit line pair BL21<0> and bar BL21<0>
for the first port. In these memory cells md00 and md10, the other
electrode of the NMOS transistor Q11 is electrically connected to the bit
line BL21<0> for the first port and the other electrode
of the NMOS transistor Q12 is electrically connected to the inverted bit
line bar BL21<0> for the first port.
Furthermore, both of the memory cells md00 and md10 are
provided between a bit line pair BL22<0> and bar BL22<0>
for the second port. In these memory cells md00 and md10, the other
electrode of the NMOS transistor Q21 is electrically connected to the bit
line BL22<0> for the second port and the other electrode
of the NMOS transistor Q22 is electrically connected to the inverted bit
line bar BL22<0> for the second port.
Both of the memory cells md01 and md11 on the same column are
provided between a bit line pair BL21<1> and bar BL21<1>
for the first port. In these memory cells md01 and md11, the other
electrode of the NMOS transistor Q11 is electrically connected to the bit
line BL21<1> for the first port and the other electrode
of the NMOS transistor Q12 is electrically connected to the inverted bit
line bar BL21<1> for the first port.
Furthermore, both of the memory cells md01 and md11 are
provided between a bit line pair BL22<1> and bar BL22<1>
for the second port. In these memory cells md10 and md11, the other
electrode of the NMOS transistor Q21 is electrically connected to the bit
line BL22<1> for the second port and the other electrode
of the NMOS transistor Q22 is electrically connected to the inverted bit
line bar BL22<1> for the second port.
In FIGS. 1 and 2, and FIG. 3 and subsequent drawings, a symbol < >
represents
a bus signal (line) and a numeral in < > corresponds to a bus signal
name. Moreover, <n-1:0> represents a signal having an n-bit width of
bus signals 0 to (n-1).
(Operation)
With reference to FIGS. 1 and 2, description will be given to a reading and
writing operation using the first port and a reading and writing operation using
the second port. For convenience of explanation, a memory cell array structure
of the 1-port memory cell array 11 and the 2-port memory cell array 12
is set to be n (rows)×m (columns).
First of all, in the case in which the reading operation of the first port
is to be executed, the read control input signal RE1 is enabled. When the
read control input signal RE1 is brought into the enable state, the row
decoder 16 for receiving a row address corresponding to the address input
bus signal AD1 through the control circuit 31 selectively sets, into
an active state, a word line WL1<i> (i=0 to n-1) for the first
port in word lines WL1<n-1:0> for the first port having n bits.
Consequently, the NMOS transistors Q11 and Q12 of each
of selected memory cells msi0 to msim of the 1-port memory cell array 11
connected to the word line WL1<i> for the first port which is
set into the active state and selected memory cells mdi0 to mdim of the
2-port memory cell array 12 are turned ON, and contents stored in each of
the selected memory cells are propagated to corresponding bit line pairs BL1
and bar BL1, and BL21 and bar BL21 for the first port.
Each of the column selectors 21 and 22 for receiving the column
address corresponding to the address input bus signal AD1 through the control
circuit 31 selects four sets of bit line pairs from m bit line pairs BL1
and bar BL1, and BL21 and bar BL21 for the first port, and
senses and amplifies them by means of an internal sense amplifier. Consequently,
the data input/output bus signal DIO11<7:4> and
the data input/output bus signal DIO12<3:0> are
output as 8-bit read data.
In the case in which the writing operation of the first port is to be executed,
next, the write control input signal WE1 is enabled. When the write control
input signal WE1 is brought into the enable state, the row decoder 16
for receiving a row address corresponding to the address input bus signal AD1
through the control circuit 31 selectively sets, into an active state, the
word line WL1<i> (i=0 to n-1) for the first port in the word lines
WL1<n-1:0> for the first port having n bits.
Consequently, the NMOS transistors Q11 and Q12 of each
of the selected memory cells msi0 to msim of the 1-port memory cell array
11 and the selected memory cells mdi0 to mdim of the 2-port memory
cell array 12 which are connected to the word line WL1<i>
for the first port set into the active state are turned ON, and the inverters 41
and 42 of each selected memory cell are electrically connected to the bit
line pairs BL1 and bar BL1, and BL21 and bar BL21 for
the first port.
At the same time, write data sent from the outside are given as the data input/output
bus signal DIO11<7:4> and the data input/output
bus signal DIO12<3:0> to/from the column selectors
21 and 22.
Each of the column selectors 21 and 22 for receiving the column
address corresponding to the address input bus signal AD1 through the control
circuit 31 selects four sets of bit line pairs from m bit line pairs BL1
and bar BL1, and BL21 and bar BL21 for the first port, and
gives the write data to the selected bit line pairs, thereby driving the selected
bit line pairs to "L" or "H". As a result, it is possible to carry out writing
based on the write data for the selected memory cell.
Then, in the case in which the reading operation of the second port is to be
executed, the read control input signal RE2 is enabled. When the read control
input signal RE2 is brought into the enable state, the row decoder 17
for receiving a row address corresponding to the address input bus signal AD2
through the control circuit 32 selectively sets, into an active state, a
word line WL2<i> (i=0 to n-1) for the second port in word lines
WL2<n-1:0> for the second port having n bits.
Consequently, the NMOS transistors Q21 and Q22 of each
of selected memory cells mdi0 to mdim of the 2-port memory cell array 12
connected to the word line WL2<i> for the second port which is
set into the active state are turned ON, and contents stored in each of the selected
memory cells are propagated to corresponding bit line pairs BL22 and bar
BL22 for the second port.
Subsequently, the column selector 23 for receiving a column
address corresponding to the address input bus signal AD2 through the control
circuit 32 selects four sets of bit line pairs from m bit line pairs BL22
and bar BL22 for the second port respectively, and senses and amplifies
them by means of an internal sense amplifier. Consequently, the data input/output
bus signal DIO2<3:0> are output as 4-bit read data.
In the case in which the writing operation of the second port is to be executed,
next, the write control input signal WE2 is enabled. When the write control
input signal WE2 is brought into the enable state, the row decoder 17
for receiving a row address corresponding to the address input bus signal AD2
through the control circuit 32 selectively sets, into an active state, the
word line WL2<i> for the second port in the word lines WL2<n-1:0>
for the second port having n bits.
Consequently, the NMOS transistors Q21 and Q22 of each
of the selected memory cells mdi0 to mdim of the 2-port memory cell array
12 connected to the word line WL2<i> for the second port
which is set into the active state are turned ON, and the inverters 41 and
42 of each selected memory cell are electrically connected to the bit line
pair BL22 and bar BL22 for the second port.
At the same time, write data sent from the outside are given as the data input/output
bus signal DIO2<3:0> to/from the column selector 23.
The column selector 23 for receiving a column address corresponding to
the address input bus signal AD2 through the control circuit 32 selects
four sets of bit line pairs from m bit line pairs BL22 and bar BL22
for the second port, and gives the write data to the selected bit line pairs, thereby
driving the selected bit line pairs to "L" or "H". As a result, it is possible
to carry out writing based on the write data for a selected memory cell.
As described above, it is possible to read and write 8-bit data which are divided
and held in high and low orders on a 4-bit unit in the 1-port memory cell array
11 and the 2-port memory cell array 12 from the first port.
Then, it is possible to read and write the lower 4-bit data which are held
in the 2-port memory cell array 12 from the second port. In this case, the
upper 4-bit data are not accessed at all.
As a result, the semiconductor storage according to the first embodiment can
divide,
on a 4-bit unit, data to be accessed on an 8-bit length unit and can access data
on a lower 4-bit unit thus obtained by the division. The lower 4-bit is accessible
from the first and second ports so that it is possible to carry out reading and
writing to meet a demand for a data dividing access.
In the first embodiment, thus, the 1-port memory cell array 11 and the
2-port memory cell array 12 including memory cells having different circuit
structures from each other can be controlled simultaneously by the row decoder
16. Therefore, it is possible to obtain a semiconductor storage having a
1-chip structure in which a single port memory cell and a 2-port memory cell having
different structures can be accessed simultaneously.
Even if the 1-port memory cell array 11 is constituted with a replacement
by a 2-port memory cell, moreover, an equivalent operation to that of the first
embodiment can be carried out. As compared with this case, an area can be decreased
because the upper 4 bits are constituted by the 1-port memory cell, and a layout
area can be decreased because it is possible to eliminate a control circuit, a
column selector and the like for the upper 4 bits which do not need to be accessed
in the second port. Since a circuit scale is thus decreased, it is possible to
reduce power consumption during an operation and a standby.
(Layout Structure)
FIGS. 3 and 4 are explanatory views showing a layout structure of a single
port memory cell MS of the 1-port memory cell array 11. FIG. 3 is an explanatory
view mainly showing a layout structure provided under a first aluminum wiring layer
as seen on a plane. FIG. 4 is an explanatory view showing a layout structure provided
above a second aluminum wiring layer as seen on a plane.
It is assumed that the inverter 41 shown in FIG. 2 is a CMOS inverter
constituted
by a PMOS transistor P1 and an NMOS transistor N1 and the inverter
42 is a CMOS inverter constituted by a PMOS transistor P2 and an
NMOS transistor N2.
As shown in FIG. 3, the PMOS transistors P1 and P2 are formed in
an N well region NW, the NMOS transistor N1 and the NMOS transistor Q11
are formed in a P well region PW1, and the NMOS transistor N2 and
the NMOS transistor Q12 are formed in a P well region PW0. The P
well region PW0 and the P well region PW1 are formed opposite to
each other with the N well region NW interposed therebetween.
In the N well region NW, the PMOS transistor P1 is constituted by a polysilicon
wiring PL1 provided across a P+ diffusion region FLP1
and the PMOS transistor P2 is constituted by a polysilicon wiring PL2
provided across a P+ diffusion region FLP2.
In the P well region PW1, the NMOS transistor N1 is constituted
by the polysilicon wiring PL1 provided across an N+ diffusion
region FLN1 and the NMOS transistor Q11 is constituted by a polysilicon
wiring PL11 provided across an N+ diffusion region FLQ11.
The polysilicon wiring PL1 is formed from the N well region NW to the P
well region PW1 and is thus shared as gates of the NMOS transistor N1
and the PMOS transistor P1.
In the P well region PW0, the NMOS transistor N2 is constituted
by the polysilicon wiring PL2 provided across an N+ diffusion
region FLN2 and the NMOS transistor Q12 is constituted by a polysilicon
wiring PL12 provided across an N+ diffusion region FLQ12.
The polysilicon wiring PL2 is formed from the N well region NW to the P
well region PW0 and is thus shared as gates of the NMOS transistor N2
and the PMOS transistor P2.
Moreover, the polysilicon wiring PL1 and the polysilicon wiring
PL12 are formed on the same straight line, the polysilicon wiring PL2
and the polysilicon wiring PL11 are formed on the same straight line, the
diffusion regions FLP1, FLN1 and FLQ12 are formed on the same
straight line in almost the same form, and the diffusion regions FLP2, FLN2
and FLQ11 are formed on the same straight line in almost the same form.
As a result, the PMOS transistor P1, the NMOS transistor N1 and
the NMOS transistor Q12 can be formed along the same straight line and the
PMOS transistor P2, the NMOS transistor N2 and the NMOS transistor
Q11 can be formed along the same straight line. Consequently, a cell height
HC1 of the single port memory cell MS can be set corresponding to two transistors.
In this specification, the cell height implies a formation length in a direction
of formation of a bit line (a longitudinal direction in the drawing) on the layout structure.
The P+ diffusion regions FLP1 and FLP2 are obtained
by implanting and diffusing a P-type impurity and the N+ diffusion regions
FLN1, FLN2, FLQ11 and FLQ12 are obtained by implanting
and diffusing an N-type impurity. In the description of FIG. 3, each diffusion
region has an upper region referred to as one of regions and a lower region referred
to as the other region with respect to the polysilicon wiring in FIG. 3.
In the P well region PW1, a ground wiring LG1 (a first layer aluminum
wiring) provided on one of the regions of the N+ diffusion region FLN1
is electrically connected to the diffusion region FLN1 through a diffusion
contact hole CH. The polysilicon wiring PL11 is electrically connected to
a word line 1WL1 (the first layer aluminum wiring) through a gate
contact hole GC, and a bit line 1BL1 (the first layer aluminum wiring)
provided on the other region of the diffusion region FLQ11 is electrically
connected to the other region of the diffusion region FLQ11 through the
diffusion contact hole CH.
The diffusion contract hole CH implies a contact hole of the diffusion region
and the first layer (aluminum) wiring, and the gate contact hole GC implies a contact
hole of the polysilicon wiring and the first layer wiring.
In the N well region NW, a power wiring LV1 (a first layer aluminum wiring)
provided on one of the regions of the diffusion region FLP1 is electrically
connected to one of the regions of the diffusion region FLP1 through a diffusion
contact hole CH, and the power wiring LV1 provided on the other region of
the diffusion region FLP2 is electrically connected to the other region
of the diffusion region FLP2 through the diffusion contact hole CH.
In the P well region PW0, the inverted bit line bar BL1 (a first
layer aluminum wiring) provided on one of the regions of the diffusion region FLQ12
is electrically connected to one of the regions of the diffusion region FLQ1
through a diffusion contact hole CH, and the word line 1WL1 provided
on the polysilicon wiring PL12 is electrically connected to the polysilicon
wiring PL12 through a gate contact hole GC. A ground wiring LG1 provided
on the other region of the diffusion region FLN2 is electrically connected
to the other region of the diffusion region FLN2 through a contact hole CH.
The aluminum wiring AL11 to be the first layer aluminum wiring extended
from the other region of the diffusion region FLN1 to the other region of
the P+ diffusion region FLP1 is electrically connected to one
of the regions of the diffusion region FLN1 through the diffusion contact
hole CH. The aluminum wiring AL11 is electrically connected to the other
region of the P+ diffusion region FLP1 and the polysilicon wiring
PL2 through a shared contact SC formed from the other region of the P+
diffusion region FLP1 to the polysilicon wiring PL2.
The aluminum wiring AL12 to be the first layer aluminum wiring extended
from one of the regions of the diffusion region FLN2 to one of the regions
of the P+ diffusion region FLP2 is electrically connected to
one of the regions of the diffusion region FLN2 through the diffusion contact
hole CH. The aluminum wiring AL12 is electrically connected to one of the
regions of the P+ diffusion region FLP2 and the polysilicon wiring
PL1 through the shared contact SC formed from one of the regions of the
P+ diffusion region FLP2 to the polysilicon, wiring PL1.
As shown in FIG. 4, a ground wiring LG2 (a second layer aluminum wiring)
is electrically connected to the lower ground wiring LG1 (not shown) through
a via hole VH1. A power wiring LV2 (the second layer aluminum wiring)
is electrically connected to the lower power wiring LV1 (not shown) through
the via hole VH1.
A word line 2WL1 (the second layer aluminum wiring) is electrically
connected to the word line 1WL1 (not shown) through the via hole
VH1, and a word line 3WL1 (a third layer aluminum wiring)
is electrically connected to the word line 2WL1 through a via hole
VH2. These word lines 1WL1 to 3WL1 constitute
the word line WL1 for the first port in FIGS. 1 and 2.
The word line 3WL1 is formed across the P well regions PW0
and PW1 and the N well region NW. The via hole VH1 implies a via
hole for connecting the first layer wiring to the second layer (aluminum) wiring,
and the via hole VH2 implies a via hole for connecting the second layer
wiring to the third layer (aluminum) wiring.
The bit line 2BL1 (the second layer aluminum wiring) is electrically
connected to the lower bit line 1BL1 (not shown) through the via
hole VH1 and the inverted bit line bar 2BL1 (the second layer
aluminum wiring) is electrically connected to the lower inverted bit line bar 1BL1
(not shown) through the via hole VH1.
The bit line pair BL1 and bar BL1 for the first port in FIGS. 1
and 2 are constituted by the bit line 2BL1, the bit line 1BL1
and the inverted bit lines bar 2BL1 and bar 1BL1.
The bit lines 2BL1 and bar 2BL1, the ground wiring
LG2 and the power wiring LV2 are formed in parallel with each other
in a longitudinal direction of FIG. 4 over the P well regions PW1 and PW0
and the N well region NW, respectively.
FIGS. 5 and 6 are explanatory views showing a layout structure of a 2-port
memory cell MD of the 2-port memory cell array 12. FIG. 5 is an explanatory
view mainly showing a layout structure provided under the first aluminum wiring
layer as seen on a plane. FIG. 6 is an explanatory view showing a layout structure
provided above the second aluminum wiring layer as seen on a plane.
It is assumed that the inverter 41 shown in FIG. 2 is a CMOS inverter
constituted
by a PMOS transistor P1 and an NMOS transistor N1 and the inverter
42 is a CMOS inverter constituted by a PMOS transistor P2 and an
NMOS transistor N2.
As shown in FIG. 5, the PMOS transistors P1 and P2 are formed in
the N well region NW, the NMOS transistor N1 and the NMOS transistors Q21
and Q22 are formed in the P well region PW1, and the NMOS transistor
N2 and the NMOS transistors Q11 and Q12 are formed in the
P well region PW0. The P well region PW0 and the P well region PW1
are formed opposite to each other with the N well region NW interposed therebetween.
In the N well region NW, the PMOS transistor P1 is constituted by a polysilicon
wiring PL1 provided across a P+ diffusion region FLP1
and the PMOS transistor P2 is constituted by a polysilicon wiring PL2
provided across a P+ diffusion region FLP2.
In the P well region PW0, the NMOS transistor N1 is constituted
by the polysilicon wiring PL1 provided across an N+ diffusion
region FLN1 and the NMOS transistors Q11 and Q12 are constituted
by a polysilicon wiring PL10 provided across N+ diffusion regions
FLQ11 and FLQ12. The polysilicon wiring PL1 is formed from
the N well region NW to the P well region PW1 and is thus shared as gates
of the NMOS transistor N1 and the PMOS transistor P1, and the polysilicon
wiring PL10 is shared as gates of the NMOS transistors Q11 and Q12.
In the P well region PW1, the NMOS transistor N2 is constituted
by the polysilicon wiring PL2 provided across an N+ diffusion
region FLN2 and the NMOS transistors Q21 and Q22 are constituted
by a polysilicon wiring PL20 provided across N+ diffusion regions
FLQ21 and FLQ22, respectively. The polysilicon wiring PL2
is formed from the N well region NW to the P well region PW0 and is thus
shared as gates of the NMOS transistor N2 and the PMOS transistor P2,
and the polysilicon wiring PL20 is shared as gates of the NMOS transistors
Q21 and Q22.
Moreover, the polysilicon wiring PL1 and the polysilicon wiring
PL20 are formed on the same straight line, the polysilicon wiring PL2
and the polysilicon wiring PL10 are formed on the same straight line, the
diffusion regions FLP1, FLN1, FLQ21 and FLQ22 are formed
on the same straight line, and the diffusion regions FLP2, FLN2,
FLQ11 and FLQ12 are formed on the same straight line.
As a result, the PMOS transistor P1 and the NMOS transistors N1,
Q21 and Q22 can be formed along the same straight line and the PMOS
transistor P2 and the NMOS transistors N2, Q11 and Q12
can be formed along the same straight line. Consequently, a cell height HC2
of the 2-port memory cell MD can be set corresponding to two transistors in the
same manner as the single port memory cell MS (HC2=HC1).
The P+ diffusion regions FLP1 and FLP2 are obtained
by implanting and diffusing a P-type impurity and the N+ diffusion regions
FLN1, FLN2, FLQ11, FLQ12, FLQ21 and FLQ22
are obtained by implanting and diffusing an N-type impurity. In the description
of FIG. 5, each diffusion region has an upper region referred to as one of regions
and a lower region referred to as the other region with respect to the polysilicon
wiring in FIG. 5.
In the P well region PW0, a ground wiring LG1 provided on one of
the regions of the N+ diffusion region FLN1 is electrically connected
to one of the regions of the diffusion region FLN1 through a diffusion contact
hole CH. The polysilicon wiring PL10 is electrically connected to a word
line 1WL1 through a gate contact hole GC, and a bit line 1BL21
(the first layer aluminum wiring) provided on the other region of the diffusion
region FLQ11 is electrically connected to the other region of the diffusion
region FLQ11 through the diffusion contact hole CH, and the inverted bit
line bar 1BL21 (the first layer aluminum wiring) provided on the
other region of the diffusion region FLQ12 is electrically connected to
the other region of the diffusion region FLQ12 through the diffusion contact
hole CH.
Furthermore, the polysilicon wiring PL1 and one of the regions
of the N+ diffusion region FLQ12 are electrically connected to
each other through the shared contact SC formed from one of the regions of the
N+ diffusion region FLQ11 to the polysilicon wiring PL1.
In the N well region NW, a power wiring LV1 provided on one of the regions
of the diffusion region FLP1 is electrically connected to one of the regions
of the diffusion region FLP1 through the diffusion contact hole CH, and
the power wiring LV1 provided on the other region of the diffusion region
FLP2 is electrically connected to the other region of the diffusion region
FLP2 through the diffusion contact hole CH.
In the P well region PW1, the bit line 1BL22 (the first
layer
aluminum wiring) provided on one of the regions of the diffusion region FLQ21
is electrically connected to one of the regions of the diffusion region FLQ21
through the diffusion contact hole CH, and the inverted bit line bar 1BL22
(the first layer aluminum wiring) provided on one of the regions of the diffusion
region FLQ22 is electrically connected to one of the regions of the diffusion
region FLQ22 through the diffusion contact hole CH.
The word line 1WL2 (the first layer aluminum wiring) provided on
the
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